As reductions in device scaling continue, the thickness of spacers and channel length are reduced, leading to a parasitic current path between the source and drain caused by source/drain punch-through, particularly in 22 nm node devices and beyond. To avoid source/drain punch-through, dopants are conventionally incorporated in source/drains by employing in-situ-doped epitaxially-grown source/drains for both NMOS and PMOS devices. Typically NMOS devices include in-situ phosphorous-doped silicon (Si) or silicon carbon (Si:C) source/drains, and PMOS devices include in-situ boron-doped silicon germanium (SiGe) source/drains.
Dopant implantation techniques, however, have not proved successful. Epitaxial growth of in-situ-doped source/drains adds additional thermal exposure to previously diffused halo and extension regions, thereby causing excessive dopant diffusion, particularly high diffusivity dopants, such as boron (B), in halo regions of NMOS devices. During high temperature epitaxial (EPI) pre-bake, significant B diffusion occurs leading to unacceptably high NMOS threshold voltage (Vt) roll-off. Lowering the EPI pre-bake temperature can reduce the short channel NMOS Vt roll-off. For example, as shown in FIG. 1, roll-off 101 at 750° C. is less than roll-off 103 at the conventional 850° C. However, even with pre-bake temperatures of about 750° C., the NMOS Vt roll-off is too large for short channel devices. Ideally, there should be virtually no roll-off, such that the lines in FIG. 1 are substantially horizontal.
Although lower NMOS EPI pre-bake temperatures reduce NMOS halo diffusion, they also prevent full recrystallization of the amorphized extension regions. As a result, cavities/voids are formed during Si:C EPI growth thereby degrading resistance of the NMOS.
A need therefore exists for methodology enabling the formation of a CMOS device with reduced NMOS halo diffusion and fully recrystallized extension regions, and the resulting short channel device.